This invention relates to Sigma Delta analog to digital converters (ADC), and, in particular, to an apparatus and a method for improving the integral non-linearity of Sigma-Delta ADCs through three point digital calibration.
Some ADCs make provision for correcting inherent errors. Such correction is commonly known as calibration which corrects for offset and gain errors. Offset is demonstrated by the ADC having a non-zero output when its input signal is zero or ground. In prior art devices the zero input is converted into a digital value, stored and subtracted from all other digital values converted thereafter. Gain error is demonstrated by the ADC having a non-ideal output, i.e., different from all 1s, when the full scale input signal is applied and offset error has been removed. In a similar manner prior art devices convert a positive reference voltage into a digital value that is offset corrected, and used to generate a gain correction factor. This gain correction factor is multiplied by all other offset corrected digital values converted thereafter.
Calibration relies upon the basic formula for a slope of a line, i.e. y=mx+b, where m represents the gain correction factor and b is the offset correction value. The ideal output for an ADC is all 1s when the input is at its full scale value. However, the actual noncalibrated full scale output of the ADC may be more or less, so its uncalibrated output is different from all 1s. In other words, instead of a slope of m, the slope is 0.5 m or 1.3 m or some other value different from the ideal. To remove gain error of the ADC others multiplied the offset calibrated output of the ADC by a gain correction factor that is the quotient of a division where the numerator represents the total resolution of the converter and the denominator is the offset corrected digital code determined from a full scale input to the ADC. As such, when an input analog signal corresponding to the actual full scale output is converted and multiplied by the calibration correction factor, the result will be the maximum output, i.e. all 1s. For example, in a three bit ADC the desired full scale output would be 111. Suppose the three bit ADC is designed to convert a full scale input of 2 volts to a digital signal. A fill scale input of 2 volts should yield a digital output of 111. Each binary code in the digital output represents one-eight of the span or 1/4 volts (i.e. LSB=0.25 V). However, one finds that when a input signal of 2 volts is applied, the offset corrected output is not 111 but rather 110. So, the three bit ADC has a gain calibration factor of 111/110, i.e. a correction factor of 7/6. So, any applied voltage signal will be corrected by subtracting offset and multiplying the correction factor (111/110) against the offset corrected value.
There are existing techniques for digital calibration to minimize offset and gain errors in Sigma Delta converters. See, for example, U.S. Pat. Nos. 4,943,807, 5,305,004 for examples of digital offset correction and unipolar gain slope correction.
The Sigma Delta modulator is the critical component in determining accuracy and linearity. In a Sigma Delta modulator with a switched capacitor integrator front-end the principal sources of non-linearity have been identified as the voltage coefficient of the capacitors (1st and 2nd order, primarily) as well as integrator leakage. Integrator leakage is due to finite integrator DC gain. This can be overcome by designing an integrator with sufficient gain for a particular application. Nonlinearity due to capacitor voltage coefficient can be addressed, to a certain extent, with a fully differential modulator structure. The fully differential signal paths allow the cancellation of first order nonlinearity due to the first order capacitor coefficient. However, the second order voltage coefficient will generate nonlinearities since they are not cancelled by these signal paths.
It has been observed that an ADC with a Sigma Delta modulator exhibits different gains for input signals of different polarities. So, negative signals will have a gain different from positive signals. It is believed that the observed difference in gains results from second order effects including the negative capacitance coefficients in the Taylor series expansion for the combined capacitance of a Sigma Delta modulator. See, for example, U.S. Pat. No. 4,918,454. Distortion due to 2nd order voltage coefficient effects are compensated for by using a capacitor interconnection scheme as shown in U.S. Pat. No. 4,918,454. There are shown polycrystalline silicon capacitors configured such that the lower plate of one capacitor is connected to the upper plate of the other capacitor and the lower plate of the other capacitor is connected to the upper plate of the first capacitor. With such a configuration, the odd ordered non-linearity contributing to the voltage coefficient errors are cancelled.
It would be desireable to have a solution to the problem of nonlinearities in ADCs without resort to a modification of the capacitor interconnection system. It would also be desireable to have a digital circuit solution to the problem of different gains of input voltages of different polarities. As is also desireable to have a piecewise linear transfer function for the ADS.